// Example netlist for an inverter simulation

/////////////////////////////////////////////////////
// Sources
// NB - You should consider including a separate file that 
//   contains the source definitions for complicated circuits
/////////////////////////////////////////////////////
// NB - pvdd is a parameter that we will define in the .ocn file
//      you may define it here by uncommenting the following line:
//parameters pvdd=1.0v
VVDD ( VDD 0 ) vsource dc=pvdd
VVSS ( VSS 0 ) vsource dc=0

// "A" bits for manual control
VVINA0 ( A0 0 ) vsource dc=0
VVINA1 ( A1 0 ) vsource dc=0
VVINA2 ( A2 0 ) vsource dc=0
VVINA3 ( A3 0 ) vsource dc=0

VVINA4 ( A4 0 ) vsource dc=0
VVINA5 ( A5 0 ) vsource dc=0
VVINA6 ( A6 0 ) vsource dc=0
VVINA7 ( A7 0 ) vsource dc=0

VVINA8 ( A8 0 ) vsource dc=0
VVINA9 ( A9 0 ) vsource dc=0
VVINA10 ( A10 0 ) vsource dc=0
VVINA11 ( A11 0 ) vsource dc=0

VVINA12 ( A12 0 ) vsource dc=0
VVINA13 ( A13 0 ) vsource dc=0
VVINA14 ( A14 0 ) vsource dc=0
VVINA15 ( A15 0 ) vsource dc=0

// "B" bits for manual control
VVINB0 ( A0 0 ) vsource dc=0
VVINB1 ( A1 0 ) vsource dc=0
VVINB2 ( A2 0 ) vsource dc=0
VVINB3 ( A3 0 ) vsource dc=0

VVINB4 ( A4 0 ) vsource dc=0
VVINB5 ( A5 0 ) vsource dc=0
VVINB6 ( A6 0 ) vsource dc=0
VVINB7 ( A7 0 ) vsource dc=0

VVINB8 ( A8 0 ) vsource dc=0
VVINB9 ( A9 0 ) vsource dc=0
VVINB10 ( A10 0 ) vsource dc=0
VVINB11 ( A11 0 ) vsource dc=0

VVINB12 ( A12 0 ) vsource dc=0
VVINB13 ( A13 0 ) vsource dc=0
VVINB14 ( A14 0 ) vsource dc=0
VVINB15 ( A15 0 ) vsource dc=0

// "CARRY0" bit for manual control
VVCIN0 ( CARRY0 0 ) vsource dc=0

/////////////////////////////////////////////////////
// Netlist: an inverter
/////////////////////////////////////////////////////
subckt inv out in vdd! gnd
XP ( out in vdd! vdd! ) PFET w=wdef l=ldef
XN ( out in gnd gnd ) NFET w=wdef l=ldef
ends inv
///////////////////////////////////////////////////////
// Netlist: a NAND gate
///////////////////////////////////////////////////////
subckt nand out inA inB vdd! gnd
P0 ( out inA vdd! vdd!) PFET w=wdef l=ldef
P1 ( out inB vdd! vdd!) PFET w=wdef l=ldef
//P2 ( out inC vdd! vdd!) PFET w=wdef l=ldef
N0 ( out inA net1 gnd) NFET w=wdef l=ldef
N1 ( net1 inB gnd gnd) NFET w=wdef l=ldef
//N2 ( net2 inC gnd gnd) NFET w=wdef l=ldef
ends nand

////////////////////////////////////////////////////
// Netlist: a clocked inverter
////////////////////////////////////////////////////
subckt clkinv out in nclk pclk vdd! gnd
M0 (net1 in vdd! vdd!) PFET w=wdef l=ldef
M1 (out pclk net1 vdd!) PFET w=wdef l=ldef
M2 (out nclk net2 gnd) NFET w=wdef l=ldef
M3 (net2 in gnd gnd) NFET w=wdef l=ldef
ends clkinv
/////////////////////////////////////////////////////
// Netlist: a D flip-flop
/////////////////////////////////////////////////////
subckt reg q d clk clkbar vdd! gnd
SE1 (out1 d clkbar clk vdd! gnd) clkinv
latch1inv (out1b out1 vdd! gnd) inv
SE2 (out1 out1b clk clkbar vdd! gnd) clkinv
SE3 (q out1 clk clkbar vdd! gnd) clkinv
latch2inv (out2b q vdd! gnd) inv
SE4 (q out2b clkbar clk vdd! gnd) clkinv
ends reg
////////////////////////////////////////////////////
// Netlist: buffer
///////////////////////////////////////////////////
subckt buff out in vdd! gnd
INV1 (net2 in vdd! gnd) inv
INV2 (out net2 vdd! gnd) inv
ends buff

///////////////////////////////////////////////////
// Netlist: XOR
//////////////////////////////////////////////////
subckt xor out a anot b bnot vdd! gnd
N10 (out anot net11 gnd) NFET w=wdef l=ldef
N11 (out b net11 gnd) NFET w=wdef l=ldef
N12 (net11 a gnd gnd) NFET w=wdef l=ldef
N13 (net11 bnot gnd gnd) NFET w=wdef l=ldef
P10 (out b net13 vdd!) PFET w=wdef l=ldef
P11 (out bnot net14 vdd!) PFET w=wdef l=ldef
P12 (net13 anot vdd! vdd!) PFET w=wdef l=ldef
P13 (net14 a vdd! vdd!) PFET w=wdef l=ldef
ends xor
/////////////////////////////////////////////////


////////////////////////////////////////////////
// Netlist: 1-bit FA
////////////////////////////////////////////////
subckt adder a b cin sum cout vdd! gnd
//Inverted signals
notA (anot a vdd! gnd) inv
notB (bnot b vdd! gnd) inv
notCin (cinnot cin vdd! gnd) inv
//Propagate
PG (prop a anot b bnot vdd! gnd) xor
//Generate
GT (gen a b vdd! gnd) nand
//Sum
notProp(nprop prop vdd! gnd) inv
S (sum prop nprop cin cinnot vdd! gnd) xor
//Carry
PC (propc prop cin vdd! gnd) nand
CARRYOUT (cout propc gen vdd! gnd) nand
ends adder
/////////////////////////////////////////

// Test Circuit

FA0 (A0 B0 CARRY0 SIGMA0 CARRY1 VDD VSS) adder
FA1 (A1 B1 CARRY1 SIGMA1 CARRY2 VDD VSS) adder
FA2 (A2 B2 CARRY2 SIGMA2 CARRY3 VDD VSS) adder
FA3 (A3 B3 CARRY3 SIGMA3 CARRY4 VDD VSS) adder

FA4 (A4 B4 CARRY4 SIGMA4 CARRY5 VDD VSS) adder
FA5 (A5 B5 CARRY5 SIGMA5 CARRY6 VDD VSS) adder
FA6 (A6 B6 CARRY6 SIGMA6 CARRY7 VDD VSS) adder
FA7 (A7 B7 CARRY7 SIGMA7 CARRY8 VDD VSS) adder

FA8 (A8 B8 CARRY8 SIGMA8 CARRY9 VDD VSS) adder
FA9 (A9 B9 CARRY9 SIGMA9 CARRY10 VDD VSS) adder
FA10 (A10 B10 CARRY10 SIGMA10 CARRY11 VDD VSS) adder
FA11 (A11 B11 CARRY11 SIGMA11 CARRY12 VDD VSS) adder

FA12 (A12 B12 CARRY12 SIGMA12 CARRY13 VDD VSS) adder
FA13 (A13 B13 CARRY13 SIGMA13 CARRY14 VDD VSS) adder
FA14 (A14 B14 CARRY14 SIGMA14 CARRY15 VDD VSS) adder
FA15 (A15 B15 CARRY15 SIGMA15 CARRY16 VDD VSS) adder
